2 - UVM Hello World Minimum Example

UVM verification environment consist of a fixed part and a variable part Fix part is the uvm_env And the veriable part are the uvm_test

UVM is implemented in class based The communication between the DUT and the environment is through interface The everything is instantiated in a top level module.

Interface

verilog
interface dut_if();
	// include any signal necessage for communicate with the DUT
endinterface: dut_if

DUT

It is the actual module

verilog
module dut(dut_if if);
// no need to say more about it
endmodule: dut

DUT instantiation

verilog
module top;
// instantiation the interface
dut_if dut_if1();

// instantiation the module and pass the interface
dut dut1(.if(dut_if1))

endmodule: top

ENV

verilog
class my_env extends uvm_env;
	// macro used for every UVM componment
	// no semicolon at the end
	uvm_component_utils(my_env)

	// constructor
	function new(string name, uvm_component parent);
		super.new(name, parent);
	endfunction:new


	// build phase
	// instantiate all the component that in our environment
	// agents, scoreboard, etc.
	function void build_phase(uvm_phase phase);
		super.build_phase(phase);
	endfunction: build_phase

	// run phase 
	// only task-based phase in UVM
	// all phase method need to take a phase agruement
	// takes the phase arguement, so we now which phase
	task run_phase(uvm_phase phase);
		
	endtask: run_phase
endclass: my_env

Run phase

In side the run phase

verilog
task run_phase(uvm_phase phase);
	// use object to start the task
	phase.raise_objection(this);	
	
	// wait 10 time unit
	#10;
	
	// stop the task
	phase.drop_object(this);
endtask: run_phase

Test

verilog
class my_test extends uvm_test;
	`uvm_component_utils(my_test)
	// declear the env
	my_env my_env_h;

	// constructor
	function new(string name, uvm_component parent);
		super.new(name, parent);
	endfunction:new

	function void build_phase(uvm_phase phase);
		// instantiation env
		// use create method to do it
		// type_id allow to override the type later designed by UVM
		// arg name and parent class
		my_env_h = my_env::type_id::create("my_env", this)
		
	endfunction: build_phase
endclass: my_test

Package

verilog
package my_pkg;
	`include "uvm_macros.svh"
	import uvm_pkg::*
	`include // any your files

endpackage: my_pkg

Test Instantiation

verilog
module top;

	import uvm_pkg::*
	import my_pkg::*

	// interface
	dut_if dut_if1();
	// module and pass interface
	dut dut1 (.if(dut_if));


	initial
	begin
		// find the my_test componment
		// start the phase executing and make the test run
		run_test("my_test");
	end