UVM verification environment consist of a fixed part and a variable part Fix part is the uvm_env And the veriable part are the uvm_test
UVM is implemented in class based The communication between the DUT and the environment is through interface The everything is instantiated in a top level module.
Interface
veriloginterface dut_if(); // include any signal necessage for communicate with the DUT endinterface: dut_if
DUT
It is the actual module
verilogmodule dut(dut_if if); // no need to say more about it endmodule: dut
DUT instantiation
verilogmodule top; // instantiation the interface dut_if dut_if1(); // instantiation the module and pass the interface dut dut1(.if(dut_if1)) endmodule: top
ENV
verilogclass my_env extends uvm_env; // macro used for every UVM componment // no semicolon at the end uvm_component_utils(my_env) // constructor function new(string name, uvm_component parent); super.new(name, parent); endfunction:new // build phase // instantiate all the component that in our environment // agents, scoreboard, etc. function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction: build_phase // run phase // only task-based phase in UVM // all phase method need to take a phase agruement // takes the phase arguement, so we now which phase task run_phase(uvm_phase phase); endtask: run_phase endclass: my_env
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